library verilog;
use verilog.vl_types.all;
entity Adder_8bits is
    port(
        LEDR            : out    vl_logic_vector(7 downto 0);
        LEDG            : out    vl_logic_vector(1 downto 0);
        SW              : in     vl_logic_vector(15 downto 0)
    );
end Adder_8bits;
